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| Freescale Semiconductor Data Sheet: Technical Data DSP56371 Rev. 4.1, 1/2007 DSP56371 Data Sheet 1 Introduction NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 DSP56371 Overview. . . . . . . . . . . . . . . . . . . . . . . 1 Signal/Connection Descriptions . . . . . . . . . . . . . 10 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Requirements . . . . . . . . . . . . . . . . . . . . . 34 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 35 DC Electrical Characteristics . . . . . . . . . . . . . . . 36 AC Electrical Characteristics. . . . . . . . . . . . . . . . 37 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External Clock Operation . . . . . . . . . . . . . . . . . . 38 Reset, Stop, Mode Select, and Interrupt Timing . 39 Serial Host Interface SPI Protocol Timing. . . . . . 42 Serial Host Interface (SHI) I2C Protocol Timing . 47 Enhanced Serial Audio Interface Timing. . . . . . . 49 Digital Audio Transmitter Timing. . . . . . . . . . . . . 54 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package Information . . . . . . . . . . . . . . . . . . . . . . 58 Design Considerations . . . . . . . . . . . . . . . . . . . . 64 Electrical Design Considerations . . . . . . . . . . . . 65 Power Consumption Benchmark . . . . . . . . . . . . 67 The DSP56371 is a high density CMOS device with 5.0-V compatible inputs and outputs. Finalized specifications may be published after further characterization and device qualifications are completed. For software or simulation models (for example, IBIS files), contact sales or go to www.freescale.com. 2 2.1 DSP56371 Overview Introduction This manual describes the DSP56371 24-bit digital signal processor (DSP), its memory, operating modes and peripheral modules. The DSP56371 is a member of (c) Freescale Semiconductor, Inc., 2004, 2005, 2006, 2007. All rights reserved. DSP56371 Overview the DSP56300 family of programmable CMOS DSPs. The DSP56371 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. Changes in core functionality specific to the DSP56371 are also described in this manual. See Figure 1. for the block diagram of the DSP56371. 5 2 12 12 11 Memory Expansion Area SHI Interface Triple Timer ESAI_1 ESAI Interface Interface GPIO EFCOP Program RAM 4K x 24 ROM 64K x 24 X Data RAM 36K x 24 ROM 32K x 24 XM_EB Y Data RAM 48K x 24 ROM 32K x 24 YM_EB 2 PIO_EB DAX PM_EB DDB YDB XDB PDB GDB Peripheral Expansion Area Address Generation Unit Six Channel DMA Unit Bootstrap ROM YAB XAB PAB DAB 24-Bit DSP56300 Core Internal Data Bus Switch Clock Generator Power Mgmt. PLL Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 x 24+5656-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter 4 JTAG OnCETM EXTAL RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1. DSP56371 Block Diagram 2.2 DSP56300 Core Description The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it. DSP56371 Data Sheet, Rev. 4.1 2 Freescale Semiconductor DSP56371 Overview The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. For a description of the DSP56300 core, see Section 2.4 DSP56300 Core Functional Blocks. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA). The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard pre-designed elements such as memories and peripherals. New modules may be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. Refer to DSP56371 User's Manual, Memory Configuration section. Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral features are described in this manual. * DSP56300 modular chassis -- 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply (QVDDL) of 1.25 V -- Object Code Compatible with the 56K core -- Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support -- Program Control with position independent code support and instruction patch support -- EFCOP running concurrently with the core, capable of executing 181 million filter taps per second at peak performance -- Six-channel DMA controller -- Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. -- Internal address tracing support and OnCE for Hardware/Software debugging -- JTAG port -- Very low-power CMOS design, fully static design with operating frequencies down to DC -- STOP and WAIT low-power standby modes * On-chip Memory Configuration -- 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM -- 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM -- 64Kx24 Bit Program and Bootstrap ROM -- 4Kx24 Bit Program RAM. -- PROM patching mechanism -- Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 44Kx24 Bit of Program RAM. * Peripheral modules -- Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 3 DSP56371 Overview -- -- -- -- -- -- slave. I2S, left justified, right justified, Sony, AC97, network and other programmable protocols Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, left justified, right justified, Sony, AC97, network and other programmable protocols Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO, support for 8, 16 and 24-bit words Triple Timer module (TEC). 11 dedicated GPIO pins Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats Pins of unused peripherals (except SHI) may be programmed as GPIO lines 2.3 DSP56371 Audio Processor Architecture This section defines the DSP56371 audio processor architecture. The audio processor is composed of the following units: * The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is described in the document 2.4 DSP56300 Core Functional Blocks The DSP56300 core provides the following functional blocks: * Data arithmetic logic unit (Data ALU) * Address generation unit (AGU) * Program control unit (PCU) * DMA controller (with six channels) * Instruction patch controller * PLL-based clock oscillator * OnCE module * Memory DSP56371 Data Sheet, Rev. 4.1 4 Freescale Semiconductor DSP56371 Overview In addition, the DSP56371 provides a set of on-chip peripherals, described in Section 2.5 Peripheral Overview. 2.4.1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of the Data ALU are as follows: * Fully pipelined 24-bit x 24-bit parallel multiplier-accumulator (MAC) * Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing) * Conditional ALU instructions * 24-bit or 16-bit arithmetic support under software control * Four 24-bit input general purpose registers: X1, X0, Y1, and Y0 * Six Data ALU registers (A2, A1, A0, B2, B1 and B0) that are concatenated into two general purpose, 56-bit accumulators (A and B), accumulator shifters * Two data bus shifter/limiter circuits 2.4.1.1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data ALU operations are stored in an accumulator. All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty (for example, without a pipeline stall). 2.4.1.2 Multiplier-Accumulator (MAC) The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result of the following form- Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP). The multiplier executes 24-bit x 24-bit, parallel, fractional multiplies, between two's-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 5 DSP56371 Overview 2.4.2 Address Generation Unit (AGU) The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around modulo and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation overhead. The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and each register triplet is composed of an address register, an offset register and a modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset adder). A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is also provided. The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output. Each Address ALU can update one address register from its respective address register file during one instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation. The modifier value is decoded in the Address ALU. 2.4.3 Program Control Unit (PCU) The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the following three hardware blocks: * Program decode controller (PDC) * Program address generator (PAG) * Program interrupt controller The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control. The PAG contains all the hardware needed for program address generation, system stack and loop control. The Program interrupt controller arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB, IRQC, IRQD and NMI) and generates the appropriate interrupt vector address. PCU features include the following: * * * * * * Position independent code support Addressing modes optimized for DSP applications (including immediate offsets) On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware DO loops Fast auto-return interrupts DSP56371 Data Sheet, Rev. 4.1 6 Freescale Semiconductor DSP56371 Overview The PCU implements its functions using the following registers: * PC--program counter register * SR--Status register * LA--loop address register * LC--loop counter register * VBA--vector base address register * SZ--stack size register * SP--stack pointer * OMR--operating mode register * SC--stack counter register The PCU also includes a hardware system stack (SS). 2.4.4 Internal Buses To provide data exchange between blocks, the following buses are implemented: * Peripheral input/output expansion bus (PIO_EB) to peripherals * Program memory expansion bus (PM_EB) to program memory * X memory expansion bus (XM_EB) to X memory * Y memory expansion bus (YM_EB) to Y memory * Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well as the memory-mapped registers in the peripherals * DMA data bus (DDB) for carrying DMA data between memories and/or peripherals * DMA address bus (DAB) for carrying DMA addresses to memories and peripherals * Program Data Bus (PDB) for carrying program data throughout the core * X memory Data Bus (XDB) for carrying X data throughout the core * Y memory Data Bus (YDB) for carrying Y data throughout the core * Program address bus (PAB) for carrying program memory addresses throughout the core * X memory address bus (XAB) for carrying X memory addresses throughout the core * Y memory address bus (YAB) for carrying Y memory addresses throughout the core All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1. 2.4.5 Direct Memory Access (DMA) The DMA block has the following features: * Six DMA channels supporting internal and external accesses * One-, two- and three-dimensional transfers (including circular buffering) * End-of-block-transfer interrupts DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 7 DSP56371 Overview * Triggering from interrupt lines and all peripherals 2.4.6 PLL-based Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division, frequency multiplication, skew elimination and the clock generator (CLKGEN), which performs low-power division and clock pulse generation. PLL-based clocking: * Allows change of low-power divide factor (DF) without loss of lock * Provides output clock with skew elimination * Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or 4), output divide factor (1, 2 or 4), and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input. This feature offers two immediate benefits: * A lower frequency clock input reduces the overall electromagnetic interference generated by a system. * The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system. NOTE The PLL will momentarily overshoot the target frequency when the PLL is first enabled or when the VCO frequency is modified. It is important that when modifying the PLL frequency or enabling the PLL that the two-step procedure defined in Section 3, DSP56371 Overview be followed. 2.4.7 On-Chip Memory The memory space of the DSP56300 core is partitioned into program memory space, X data memory space and Y data memory space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can not be expanded off-chip. There is an instruction patch module. The patch module is used to patch program ROM. The memory switch mode is used to increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM). There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and Y ROM (32K x 24-bit). More information on the internal memory is provided in the DSP56371 User's Manual, Memory section. 2.4.8 Off-Chip Memory Expansion Memory cannot be expanded off-chip. There is no external memory bus. DSP56371 Data Sheet, Rev. 4.1 8 Freescale Semiconductor DSP56371 Overview 2.5 Peripheral Overview The DSP56371 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core features previously discussed, the DSP56371 provides the following peripherals: * As many as 39 dedicate or user-configurable general purpose input/output (GPIO) signals * Timer/event counter (TEC) module, containing three independent timers * Memory switch mode in on-chip memory * Four external interrupt/mode control lines and one external non-maskable interrupt line * Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the I2S, Sony, AC97, network and other programmable protocols * A second enhanced serial audio interface (ESAI_1) with up to four receivers and up to six transmitters, master or slave, using the I2S, Sony, AC97, network and other programmable protocols. * * Serial host interface (SHI) using SPI and I2C protocols, with multi-master capability, 10-word receive FIFO and support for 8-, 16- and 24-bit words A Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats 2.5.1 General Purpose Input/Output (GPIO) The DSP56371 provides 11 dedicated GPIO and 28 programmable signals that can operate either as GPIO pins or peripheral pins (ESAI, ESAI_1, DAX, and TEC). The signals are configured as GPIO after hardware reset. Register programming techniques for all GPIO functionality among these interfaces are very similar and are described in the following sections. 2.5.2 Triple Timer (TEC) This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general purpose 24-bit timer/event counters, each one having its own register set. Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Two of the three timers can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers after a specified number of events (clocks) occurred. Two of the three timers connect to the external world through bidirectional pins (TIO0, TIO1). When a TIO pin is configured as input, the timer functions as an external event counter or can measure external pulse width/signal period. When a TIO pin is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator. When a TIO pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to DSP56371 User's Manual, Triple Timer Module section. 2.5.3 Enhanced Serial Audio Interface (ESAI) The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other DSPs, microprocessors and peripherals that DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 9 Signal/Connection Descriptions implement the Motorola SPI serial protocol. The ESAI consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to DSP56371 User's Manual, Enhanced Serial Audio Interface (ESAI) section. 2.5.4 Enhanced Serial Audio Interface 1 (ESAI_1) The ESAI_1 is a second ESAI interface. The ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer to DSP56371 User's Manual, Enhanced Serial Audio Interface (ESAI_1) section. 2.5.5 Serial Host Interface (SHI) The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface directly to either of two well-known and widely used synchronous serial buses: the Motorola serial peripheral interface (SPI) bus and the Philips inter-integrated-circuit control (I2C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a slave or a single-master device. To minimize DSP overhead, the SHI supports single-, double- and triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead for data reception. For more information on the SHI, refer to DSP56371 User's Manual, Serial Host Interface section. 2.5.6 Digital Audio Transmitter (DAX) The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. For more information on the DAX, refer to DSP56371 User's Manual, Digital Audio section. 3 3.1 Signal/Connection Descriptions Signal Groupings The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 1. and illustrated in Figure 2. The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for this feature is added to the signal descriptions of those inputs. DSP56371 Data Sheet, Rev. 4.1 10 Freescale Semiconductor Signal/Connection Descriptions Table 1. DSP56374 Functional Signal Groupings Functional Group Power (VDD) Ground (GND) Scan Pins Clock and PLL Interrupt and mode control SHI ESAI ESAI_1 SPDIF Transmitter (DAX) Dedicated GPIO Timer JTAG/OnCE Port Note: 1. 2. 3. 4. Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Port F signals are the dedicated GPIO port signals. Number of Signals 12 12 1 2 5 5 Port C1 Port Port E2 D3 12 12 2 11 2 4 Detailed Description Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Port F4 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 11 Signal/Connection Descriptions Pinout (80 pin package) GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 Port F MOSI/HA0 SS/HA2 MISO/HDA SCK/SCL HREQ TIO0 TIO1 SHI TIMER ESAI Port C SPDIF TRANSMITTER (DAX) ADO [PD1] ACI [PD0] Port D SCKT FST HCKT SCKR FSR HCKR SDO0 SDO1 SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 SCKT_1 FST_1 HCKT_1 SCKR_1 FSR_1 HCKR_1 SDO0_1 SDO1_1 SDO2_1/SDI3_1 SDO3_1/SDI2_1 SDO4_1/SDI1_1 SDO5_1/SDI0_1 INTERRUPTS IRQA/MODA IRGB/MODB IRQC/MODC IRQD/MODD RESET Port E PLL AND CLOCK EXTAL NMI/PINIT PLL_VDD(3) PLL_GND(3) ESAI_1 CORE POWER CORE_VDD (4) CORE_GND (4) OnCE/JTAG TDI TCLK TDO TMS PERIPHERAL I/O POWER IO_VDD (5) IO_GNDS (5) SCAN SCAN Figure 2. Signals Identified by Functional Group DSP56371 Data Sheet, Rev. 4.1 12 Freescale Semiconductor Signal/Connection Descriptions 3.2 Power Table 2. Power Inputs Power Name Description PLLA_VDD (1) PLL Power-- The voltage (3.3 V) should be well-regulated and the input should be provided with an PLLP_VDD(1) extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate external decoupling capacitors. PLLD_VDD (1) PLL Power-- The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate external decoupling capacitors. CORE_VDD (4) Core Power--The voltage (1.25 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate decoupling capacitors. IO_VDD (5) SHI, ESAI, ESAI_1, DAX and Timer I/O Power --The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail. This is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer I/O. The user must provide adequate external decoupling capacitors. 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 ESAI SDO5_SDI0_PC7 IO_GND IO_VDD SDO3_SDI2_PC8 SDO2_SDI3_PC9 SDO1_PC10 SDO0_PC11 CORE_VDD PF8 PF6 PF7 CORE_GND PF2 PF3 PF4 PF5 IO_VDD PF1 PF0 IO_GND 1 DAX ESAI_1 60 61 8 0 SDO5_SDI0_PC6 FST_PC4 FSR_PC1 SCKT_PC3 SCKR_PC0 IO_VDD IO_GND HCKT_PC5 HCKR_PC2 CORE_VDD ACI_PD0 ADO_PD1 CORE_GND HCKR_PE2 HCKT_PE5 IO_GND IO_VDD SCKR_PE0 SCKT_PE3 FSR_PE1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 13 GPIO Int/Mod 48 47 14 46 15 45 16 44 17 43 18 PLL Timer OnCE SHI 42 19 41 FST_PE4 SDO5_SDI0_PE6 SDO4_SDI1_PE7 SDO3_SDI2_PE8 SDO2_SDI3_PE9 SDO1_PE10 SDO0_PE11 CORE_GND CORE_VDD MODB_IRQA MODB_IRQB MODC_IRQC MODD_IRQD RESET_B PINIT_NMI EXTAL PLLD_VDD PLLD_GND PLLP_GND PLLP_VDD 20 PF9 SCAN PF10 IO_GND IO_VDD TIO0_PB0 TIO1_PB1 CORE_GND28 CORE_VDD29 TDO TDI TCK TMS MOSI_HA0 MISO_SDA SCK_SCL SS_HA2 HREQ PLLA_VDD PLLA_GND40 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 38 39 1.25V 3.3V Figure 3. VDD Connections DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 13 Signal/Connection Descriptions 3.3 Ground Table 3. Grounds Description PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. The user must provide adequate external decoupling capacitors. Ground Name PLLA_GND(1) PLLP_GND(1) PLLD_GND(1) PLL Ground--The PLL ground should be provided with an extremely low-impedance path to ground. The user must provide adequate external decoupling capacitors. CORE_GND (4) Core Ground--The Core ground should be provided with an extremely low-impedance path to ground. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. IO_GND (5) SHI, ESAI, ESAI_1, DAX and Timer I/O Ground--IO_GND is an isolated ground for the SHI, ESAI, ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. 3.4 SCAN Table 4. SCAN Signals Signal Name SCAN Type Input State During Reset Input Signal Description SCAN--Manufacturing test pin. This pin should be pulled low. Internal Pull down resistor. 3.5 Clock and PLL Table 5. Clock and PLL Signals Signal Name EXTAL Type Input State during Reset Input Signal Description External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. This input is 5 V tolerant. PINIT/NMI Input Input PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock. Internal Pull up resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 14 Freescale Semiconductor Signal/Connection Descriptions 3.6 Interrupt and Mode Control Table 6. Interrupt and Mode Control Signal Name MODA/IRQA Type Input State During Reset Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. Internal Pull up resistor. This input is 5 V tolerant. The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 15 Signal/Connection Descriptions Table 6. Interrupt and Mode Control (continued) Signal Name MODB/IRQB Type Input State During Reset Input Signal Description Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. Internal Pull up resistor. This input is 5 V tolerant. MODC/IRQC Input Input Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. Internal Pull up resistor. This input is 5 V tolerant. MODD/IRQD Input Input Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. Internal Pull up resistor. This input is 5 V tolerant. RESET Input Input Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. Internal Pull up resistor. This input is 5 V tolerant. 3.7 Serial Host Interface The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. DSP56371 Data Sheet, Rev. 4.1 16 Freescale Semiconductor Signal/Connection Descriptions Table 7. Serial Host Interface Signals Signal Name SCK Signal Type Input or output State during Reset Signal Description Tri-stated SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VDD through a pull-up resistor. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up in this state. Internal Pull up resistor. This input is 5 V tolerant. SCL Input or output MISO Input or output Tri-stated SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VDD through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and it is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up in this state. Internal Pull up resistor. This input is 5 V tolerant. SDA Input or open-drain output DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 17 Signal/Connection Descriptions Table 7. Serial Host Interface Signals (continued) Signal Name MOSI Signal Type Input or output State during Reset Signal Description Tri-stated SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up in this state. Internal Pull up resistor. This input is 5 V tolerant. HA0 Input SS Input Tri-stated SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software and individual reset. Thus, there is no need for an external pull-up in this state. Internal Pull up resistor. This input is 5 V tolerant. HA2 Input HREQ Input or Output Tri-stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for an external pull-up in this state. Internal Pull up resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 18 Freescale Semiconductor Signal/Connection Descriptions 3.8 Enhanced Serial Audio Interface Table 8. Enhanced Serial Audio Interface Signals Signal Name HCKR Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (for example, for external digital to analog converters [DACs]) or as an additional system clock. Port C2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. HCKT Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (for example, for external DACs) or as an additional system clock. Port C5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC2 Input, output, or disconnected PC5 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 19 Signal/Connection Descriptions Table 8. Enhanced Serial Audio Interface Signals (continued) Signal Name FSR Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC1 Input, output, or disconnected Port C1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. FST Input or output GPIO disconnected Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC4 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 20 Freescale Semiconductor Signal/Connection Descriptions Table 8. Enhanced Serial Audio Interface Signals (continued) Signal Name SCKR Signal Type Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, output, or disconnected Port C0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKT Input or output GPIO disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO5 SDI0 PC6 Output Input Input, output, or disconnected GPIO disconnected Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC3 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 21 Signal/Connection Descriptions Table 8. Enhanced Serial Audio Interface Signals (continued) Signal Name SDO4 SDI1 PC7 Signal Type Output Input Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. Port C8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO2 Output GPIO disconnected Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. Port C9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI2 Input PC8 Input, output, or disconnected SDI3 Input PC9 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 22 Freescale Semiconductor Signal/Connection Descriptions Table 8. Enhanced Serial Audio Interface Signals (continued) Signal Name SDO1 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. Port C10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0 Output GPIO disconnected Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. Port C11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PC10 Input, output, or disconnected PC11 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 23 Signal/Connection Descriptions 3.9 Enhanced Serial Audio Interface_1 Table 9. Enhanced Serial Audio Interface_1 Signals Signal Name HCKR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (for example, for external digital to analog converters [DACs]) or as an additional system clock. Port E2--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. HCKT_1 Input or output GPIO disconnected High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (for example, for external DACs) or as an additional system clock. Port E5--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE2 Input, output, or disconnected PE5 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 24 Freescale Semiconductor Signal/Connection Descriptions Table 9. Enhanced Serial Audio Interface_1 Signals Signal Name FSR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR_1 register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR_1 register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PE1 Input, output, or disconnected Port E1--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. FST_1 Input or output GPIO disconnected Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST_1 is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI_1 transmit clock control register (TCCR_1). Port E4--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE4 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 25 Signal/Connection Descriptions Table 9. Enhanced Serial Audio Interface_1 Signals Signal Name SCKR_1 Signal Type Input or output State during Reset GPIO disconnected Signal Description Receiver Serial Clock_1--SCKR_1 provides the receiver serial bit clock for the ESAI_1. The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR_1 register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR_1 register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR_1 register, synchronized by the frame sync in normal mode or the slot in network mode. PE0 Input, output, or disconnected Port E0--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SCKT_1 Input or output GPIO disconnected Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI_1. SCKT_1 is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E3--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO5_1 Output GPIO disconnected Serial Data Output 5_1--When programmed as a transmitter, SDO5_1 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0_1 is used to receive serial data into the RX0 serial receive shift register. Port E6--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PE3 Input, output, or disconnected SDI0_1 Input PE6 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 26 Freescale Semiconductor Signal/Connection Descriptions Table 9. Enhanced Serial Audio Interface_1 Signals Signal Name SDO4_1 Signal Type Output State during Reset GPIO disconnected Signal Description Serial Data Output 4_1--When programmed as a transmitter, SDO4_1 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1_1 is used to receive serial data into the RX1 serial receive shift register. Port E7--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO3_1 Output GPIO disconnected Serial Data Output 3--When programmed as a transmitter, SDO3_1 is used to transmit data from the TX3 serial transmit shift register. Serial Data Input 2--When programmed as a receiver, SDI2_1 is used to receive serial data into the RX2 serial receive shift register. Port E8--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO2_1 Output GPIO disconnected Serial Data Output 2--When programmed as a transmitter, SDO2_1 is used to transmit data from the TX2 serial transmit shift register. Serial Data Input 3--When programmed as a receiver, SDI3_1 is used to receive serial data into the RX3 serial receive shift register. Port E9--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDI1_1 Input PE7 Input, output, or disconnected SDI2_1 Input PE8 Input, output, or disconnected SDI3_1 Input PE9 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 27 Signal/Connection Descriptions Table 9. Enhanced Serial Audio Interface_1 Signals Signal Name SDO1_1 PE10 Signal Type Output Input, output, or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 1--SDO1_1 is used to transmit data from the TX1 serial transmit shift register. Port E10--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. SDO0_1 PE11 Output Input, output, or disconnected GPIO disconnected Serial Data Output 0--SDO0_1 is used to transmit data from the TX0 serial transmit shift register. Port E11--When the ESAI_1 is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 28 Freescale Semiconductor Signal/Connection Descriptions 3.10 SPDIF Transmitter Digital Audio Interface Table 10. Digital Audio Interface (DAX) Signals Signal Name ACI Type Input State During Reset GPIO Disconnected Signal Description Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). Port D0--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. ADO Output GPIO Disconnected Digital Audio Data Output--This signal is an audio and non-audio output in the form of AES/SPDIF, CP340 and IEC958 data in a biphase mark format. Port D1--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PD0 Input, output, or disconnected PD1 Input, output, or disconnected DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 29 Signal/Connection Descriptions 3.11 Dedicated GPIO Interface Table 11. Dedicated GPIO Signals Signal Name PF0 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port F0--this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF1 Input, output, or disconnected GPIO disconnected Port F1-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF2 Input, output, or disconnected GPIO disconnected Port F2-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF3 Input, output, or disconnected GPIO disconnected Port F3--this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF4 Input, output, or disconnected GPIO disconnected Port F4-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF5 Input, output, or disconnected GPIO disconnected Port F5--this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF6 Input, output, or disconnected GPIO disconnected Port F6--this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 30 Freescale Semiconductor Signal/Connection Descriptions Table 11. Dedicated GPIO Signals (continued) Signal Name PF7 Type Input, output, or disconnected State During Reset GPIO disconnected Signal Description Port F7-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF8 Input, output, or disconnected GPIO disconnected Port F8-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF9 Input, output, or disconnected GPIO disconnected Port F9-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. PF10 Input, output, or disconnected GPIO disconnected Port F10-- this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. Internal Pull down resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 31 Signal/Connection Descriptions 3.12 Timer Table 12. Timer Signal Signal Name TIO0 Type Input or Output State during Reset Signal Description GPIO Input Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to VDD through a pull-up resistor in order to ensure a stable logic level at this input. Internal Pull down resistor. This input is 5 V tolerant. TIO1 Input or Output GPIO Input Timer 1 Schmitt-Trigger Input/Output--When timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 1 control/status register (TCSR1). If TIO1 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vdd through a pull-up resistor in order to ensure a stable logic level at this input. Internal Pull down resistor. This input is 5 V tolerant. DSP56371 Data Sheet, Rev. 4.1 32 Freescale Semiconductor Maximum Ratings 3.13 JTAG/OnCE Interface Table 13. JTAG/OnCE Interface Signal Name TCK Signal Type Input State during Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. Internal Pull up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Internal Pull up resistor. This input is 5 V tolerant. TDO Output Tri-state Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. Internal Pull up resistor. This input is 5 V tolerant. TMS Input Input 4 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (for example, either GND or VDD). The suggested value for a pull-up or pull-down resistor is 4.7 k. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 33 Power Requirements Table 14. Maximum Ratings Rating1 Supply Voltage Symbol VCORE_VDD, VPLLD_VDD VPLLP_VDD, VIO_VDD, VPLLA_VDD, All "5.0V tolerant" input voltages Current drain per pin excluding VDD and GND (Except for pads listed below) SCK_SCL ACI_PD0,ADO_PD1 TDO Operating temperature Storage temperature Note: 1. GND = 0 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50PF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. Operating temperature qualified for automotive applications. Value1, 2 Unit V -0.3 to + 1.6 -0.3 to + 4.0 GND - 0.3 to 5.5V 12 16 24 24 -40 to +115 V V mA mA mA mA VIN I ISCK IDAX Ijtag range3 TJ TSTG -55 to +125 C C 5 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is recommended to be made between the DSP56371 IO_VDD and CORE_VDD power pins. IO VDD External Schottky Diode CORE VDD To prevent a high current condition upon power up, the IOVDD must be applied ahead of the CORE VDD as shown below if the external Schottky is not used. CORE VDD IO VDD DSP56371 Data Sheet, Rev. 4.1 34 Freescale Semiconductor Thermal Characteristics 6 Thermal Characteristics Table 15. Thermal Characteristics Characteristic Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Note: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Symbol RJA or JA RJC or JC TQFP Value 39 18.25 Unit C/W C/W 7 DC Electrical Characteristics Table 16. DC ELECTRICAL CHARACTERISTICS4 Characteristics Supply voltages * Core (core_vdd) * PLL (plld_vdd) Supply voltages * Vio_vdd * PLL (pllp_vdd) * PLL (plla_vdd) Input high voltage * All pins Symbol VDD Min 1.2 Typ 1.25 Max 1.31 Unit V VDDIO 3.14 3.3 3.461 V V VIH 2.0 -- VIO_VDD+2V Note: All 3.3 V supplies must rise prior to the rise of the 1.25 V supplies to avoid a high current condition and possible system damage. Input low voltage * All pins Input leakage current (All pins) Clock pin Input Capacitance (EXTAL) High impedance (off-state) input current (@ 3.46 V) Output high voltage IOH = -5 mA Output low voltage IOL = 5 mA Internal supply current1 at internal clock of 181MHz * In Normal mode VIL IIN CIN ITSI VOH VOL -84 2.4 -- -0.3 -- -- -- 3.749 -- -- -- 84 -- 0.4 0.8 84 V A pF A V V ICCI -- 99 200 mA DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 35 AC Electrical Characteristics Table 16. DC ELECTRICAL CHARACTERISTICS4 Characteristics * In Wait mode * In Stop mode 3 Symbol ICCW ICCS CIN Min -- -- -- Typ 48 2.5 -- Max 150 82 10 Unit mA mA pF Input capacitance4 Note: 1. Section 3, Power Consumption Considerations provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (for example, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCORE_VDD = 1.30 V, VIO_VDD) = 3.46V at TJ = 115C. 2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (for example, not allowed to float). 3. Periodically sampled and not 100% tested 4. TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL=50pF 8 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56371 output levels are measured with the production test machine VOL and VOH reference levels set at 1.0V and 1.8V, respectively. NOTE Although the minimum value for the frequency of EXTAL is 0 MHz (PLL bypassed), the device AC test conditions are 5 MHz and rated speed. DSP56371 Data Sheet, Rev. 4.1 36 Freescale Semiconductor Internal Clocks 9 No. 1 2 3 Internal Clocks Table 17. INTERNAL CLOCKS Characteristics Comparison Frequency Input Clock Frequency Output clock Frequency (with PLL enabled)2,3 Output clock Frequency (with PLL disabled)2,3 Duty Cycle Symbol Fref1 FIN FOUT Tc 4 5 FOUT Tc -- 75 13.3 -- 40 1000/Etc 50 -- 60 Min 5 Typ -- Fref*NR (1000/Etc x MF x FM)/ (PDF x DF x OD) -- MHZ ns MHZ % Max 20 UNIT MHZ Condition Fref = FN/NR NR is input divider value FOUT = FVCO/NO where NO is output divider value -- FVCO=300MHZ ~600MHZ Note: 1 See users manual for definition. 2 DF = Division Factor Ef = External frequency MF = Multiplication Factor PDF = Predivision Factor FM= Feedback Multiplier OD = Output Divider Tc = internal clock period 3 Maximum frequency will vary depending on the ordered part number. 10 External Clock Operation . The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL (see Figure 4.). VIH EXTAL VIL ETH 6 8 ETL 7 ETC Midpoint Note: The midpoint is 0.5 (VIH + VIL). Figure 4. External Clock Timing DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 37 Reset, Stop, Mode Select, and Interrupt Timing Table 18. Clock Operation 150 and 181 MHz Values 150 MHz No. 6 7 8 Characteristics EXTAL input high 1,2 (40% to 60% duty cycle) EXTAL input low1,2 (40% to 60% duty cycle) EXTAL cycle time2 * With PLL disabled * With PLL enabled Instruction cycle time= ICYC = TC3 * With PLL disabled * With PLL enabled 1. 2. 3. 4. 181 MHz Min 2.75ns 2.75ns Max 100ns 100ns Symbol Min Eth Etl Etc 6.66ns 6.66ns Icyc 6.66ns 6.66ns inf 13.0ns 5.52ns 5.52ns inf 13.0ns inf 200ns 5.52ns 5.52ns inf 200ns 3.33ns 3.33ns Max 100ns 100ns 9 Note: Measured at 50% of the input transition The maximum value for PLL enabled is given for minimum VCO and maximum MF. The maximum value for PLL enabled is given for minimum VCO and maximum DF. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 11 No. 10 11 Reset, Stop, Mode Select, and Interrupt Timing Table 19. Reset, Stop, Mode Select, and Interrupt Timing Characteristics Delay from RESET assertion to all output pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled 12 13 Syn reset setup time from RESET * Maximum Syn reset de assert delay time * Minimum * Maximum(PLL enabled) Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width 2 xTC 2 xTC Expression -- Min -- Max 11 Unit ns 2 x TC 2 x TC 11.1 11.1 -- -- ns ns TC 2x TC (2xTC)+TLOCK -- 11.1 5.0 10.0 10.0 11.1 11.1 5.5 -- -- -- -- -- ns ns ms ns ns ns ns 14 15 16 17 Minimum edge-triggered interrupt request deassertion width DSP56371 Data Sheet, Rev. 4.1 38 Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Table 19. Reset, Stop, Mode Select, and Interrupt Timing (continued) No. 18 19 Characteristics Delay from interrupt trigger to interrupt code execution. Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 * PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 20 * Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Interrupt Requests Rate * ESAI, ESAI_1, SHI, DAX, Timer * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 22 DMA Requests Rate * Data read from ESAI, ESAI_1, SHI, DAX * Data write to ESAI, ESAI_1, SHI, DAX * Timer * IRQ, NMI (edge trigger) Note: 1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms. 3. Periodically sampled and not 100% tested 4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When the VDD is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. Expression 10 xTC + 5 Min 60.0 Max Unit ns 9+(128Kx TC) 25x TC 704 138 -- -- us ns 9+(128KxTC)+Tlock (25 x TC)+Tlock 10 x TC + 3.0 5.7 5 59.0 ms ms ns 21 12 x TC 8 x TC 8 x TC 12 c TC 6 x TC 7 x TC 2 x TC 3 x TC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 39 Reset, Stop, Mode Select, and Interrupt Timing VIH RESET 11 10 All Pins Reset Value 13 Figure 5. Reset Timing RESET VIH 14 15 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQD, NMI Figure 6. Recovery from Stop State Using IRQA Interrupt Service IRQA, IRQB, IRQC, IRQD, NMI 16 IRQA, IRQB, IRQC, IRQD, NMI 17 Figure 7. External Interrupt Timing (Negative Edge-Triggered) DSP56371 Data Sheet, Rev. 4.1 40 Freescale Semiconductor Serial Host Interface SPI Protocol Timing IRQA, IRQB, IRQC, IRQD, NMI 19 18 a) First Interrupt Instruction Execution General Purpose I/O 20 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O Figure 8. External Fast Interrupt Timing 12 No. 23 24 Serial Host Interface SPI Protocol Timing Table 20. Serial Host Interface SPI Protocol Timing Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min) Serial clock high period Mode Master Master Slave Expressions 10.0 x TC + 9 -- 2.0 x TC + 19.6 -- 2.0 x TC + 19.6 -- -- 2.0 x TC + 12.6 -- -- -- 3.0 x TC -- -- 3.0 x TC + 26.1 Min 64.0 29.5 27.5 29.5 27.5 -- -- 34.4 10.0 12.0 0 22.4 5 -- 50.0 Max -- -- -- -- -- 10 10 -- -- -- -- -- -- 9 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 Serial clock low period Master Slave 26 Serial clock rise/fall time Master Slave 27 SS assertion to first SCK edge CPHA = 0 CPHA = 1 Slave Slave Slave Master/Slave Master/Slave Slave Slave Master/Slave 28 29 30 31 32 33 Last SCK edge to SS not asserted Data input valid to SCK edge (data input set-up time) SCK last sampling edge to data input not valid SS assertion to data out active SS deassertion to data high impedance2 SCK edge to data out valid (data out delay time) DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 41 Serial Host Interface SPI Protocol Timing Table 20. Serial Host Interface SPI Protocol Timing (continued) No. 34 35 36 37 38 39 40 41 42 43 Note: 1. 2. 3. 4. 5. VCORE_VDD = 1.2 5 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF Periodically sampled, not 100% tested All times assume noise free inputs All times assume internal clock frequency of 150 MHz Equation applies when the result is positive TC Characteristics1,3,4 SCK edge to data out not valid (data out hold time) SS assertion to data out valid (CPHA = 0) First SCK sampling edge to HREQ output deassertion Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) SS deassertion to HREQ output not deasserted (CPHA = 0) SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time) HREQ assertion width Mode Master/Slave Slave Slave Slave Slave Slave Master Master Master Master Expressions 2.0 x TC -- 3.0 x TC + 30 4.0 x TC 3.0 x TC + 30 2.0 x TC 0.5 x TSPICC + 3.0 x TC + 5 -- -- 3.0 x TC Min 12.0 -- 50 52.2 46.6 12.7 63.0 0 0 20.0 Max -- 15.0 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns Figure 9. SPI Master Timing (CPHA = 0) DSP56371 Data Sheet, Rev. 4.1 42 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB 29 LSB Valid 34 LSB 30 23 26 26 26 23 26 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 43 Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Output) 24 25 SCK (CPOL = 1) (Output) 29 30 MISO (Input) MSB Valid 33 MOSI (Output) 40 42 HREQ (Input) 43 MSB 41 LSB Valid 34 LSB 29 30 26 23 26 26 23 26 Figure 10. SPI Master Timing (CPHA = 1) DSP56371 Data Sheet, Rev. 4.1 44 Freescale Semiconductor Serial Host Interface SPI Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 35 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 38 34 MSB 29 30 33 34 LSB 32 23 26 26 26 23 26 39 28 Figure 11. SPI Slave Timing (CPHA = 0) DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 45 Serial Host Interface (SHI) I2C Protocol Timing SS (Input) 25 24 SCK (CPOL = 0) (Input) 27 24 25 SCK (CPOL = 1) (Input) 33 31 MISO (Output) 29 30 MOSI (Input) MSB Valid 36 HREQ (Output) LSB Valid 37 MSB 29 30 33 34 32 LSB 26 26 26 23 26 28 Figure 12. SPI Slave Timing (CPHA = 1) 13 Serial Host Interface (SHI) I2C Protocol Timing Table 21. SHI I2C Protocol Timing Standard I2C* Characteristics1 SCL clock frequency SCL clock cycle Bus free time Start condition set-up time Start condition hold time SCL low period SCL high period SCL and SDA rise time SCL and SDA fall time Symbol/ Expression FSCL TSCL TBUF TSUSTA THD;STA TLOW THIGH TR TF DSP56371 Data Sheet, Rev. 4.1 Standard Min -- 10 4.7 4.7 4.0 4.7 4.0 -- -- Max 100 -- -- -- -- -- -- 5 5 Fast-Mode Min -- 2.5 1.3 0.6 0.6 1.3 1.3 -- -- Max 400 -- -- -- -- -- -- 5 5 kHz s s s s s s ns ns Unit No. 44 44 45 46 47 48 49 50 51 46 Freescale Semiconductor Serial Host Interface (SHI) I2C Protocol Timing Table 21. SHI I2C Protocol Timing (continued) Standard I2C* Characteristics1 Data set-up time Data hold time DSP clock frequency SCL low to data out valid Stop condition setup time HREQ in deassertion to last SCL edge (HREQ in set-up time) First SCL sampling edge to HREQ output deassertion Symbol/ Expression TSU;DAT THD;DAT FOSC TVD;DAT TSU;STO tSU;RQI TNG;RQO 4 x TC + 30 59 Last SCL edge to HREQ output not deasserted TAS;RQO 2 x TC + 30 60 HREQ in assertion to first SCL edge TAS;RQI 0.5 x TI2CCP -0.5 x TC - 21 61 Note: 1. 2. 3. 4. 5. VCORE_VDD = 1.2 5 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF Pull-up resistor: R P (min) = 1.5 kOhm Capacitive load: C b (max) = 50 pF All times assume noise free inputs All times assume internal clock frequency of 180MHz Standard Min 250 0.0 10.6 -- 4.0 0.0 Max -- -- -- 3.4 -- -- Fast-Mode Min 100 0.0 28.5 -- 0.6 0.0 Max -- 0.9 -- 0.9 -- -- Unit No. 52 53 54 55 56 57 58 ns s MHz s s ns -- 52 -- 52 ns 52 -- 52 -- ns 4327 0.0 -- -- 927 0.0 -- -- ns ns First SCL edge to HREQ in not asserted (HREQ in hold time.) tHO;RQI 13.1 Programming the Serial Clock The programmed serial clock cycle, T I CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). 2 The expression for T I CCP is 2 T I2CCP = [TC x 2 x (HDM[7:0] + 1) x (7 x (1 - HRS) + 1)] Eqn. 1 where -- HRS is the pre-scaler rate select bit. When HRS is cleared, the fixed divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed. -- HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 47 Enhanced Serial Audio Interface Timing In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC (if HDM[7:0] = $02 and HRS = 1) Eqn. 2 to 4096 x TC (if HDM[7:0] = $FF and HRS = 0) 2 Eqn. 3 The programmed serial clock cycle (TI CCP ), SCL rise time (TR), should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 22. 44 46 SCL 50 45 52 SDA Stop Start 47 61 60 HREQ MSB 58 57 59 LSB 55 ACK 56 Stop 51 53 49 48 Figure 13. I2C Timing 14 No. Enhanced Serial Audio Interface Timing Table 22. Enhanced Serial Audio Interface Timing Characteristics1, 2, 3 Symbol tSSICC Expression 4 x Tc 4 x Tc Min 22.3 22.3 12.0 12.0 12.0 12.0 -- -- -- -- Max -- -- -- -- -- -- 37.0 22.0 37.0 22.0 x ck i ck a x ck i ck a ns ns ns Condition4 x ck i ck ns Unit ns 62 Clock cycle5 63 Clock high period * For internal clock * For external clock 64 Clock low period * For internal clock * For external clock 65 SCKR edge to FSR out (bl) high 66 SCKR edge to FSR out (bl) low tSSICCH 2 x Tc 2 x Tc tSSICCL 2 x Tc 2 x Tc -- -- -- -- DSP56371 Data Sheet, Rev. 4.1 48 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 22. Enhanced Serial Audio Interface Timing (continued) No. Characteristics1, 2, 3 Symbol -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Expression -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min -- -- -- -- -- -- -- -- 12.0 19.0 5.0 3.0 2.0 23.0 2.0 23.0 3.0 0.0 0.0 19.0 6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 26.5 21.0 31.0 16.0 Condition4 x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 67 SCKR edge to FSR out (wr) high6 68 SCKR edge to FSR out (wr) low6 69 SCKR edge to FSR out (wl) high 70 SCKR edge to FSR out (wl) low 71 Data in setup time before SCKR (SCK in synchronous mode) edge 72 Data in hold time after SCKR edge 73 FSR input (bl, wr) high before SCKR edge 6 74 FSR input (wl) high before SCKR edge 75 FSR input hold time after SCKR edge 76 Flags input setup before SCKR edge 77 Flags input hold time after SCKR edge 78 SCKT edge to FST out (bl) high 79 SCKT edge to FST out (bl) low 80 SCKT edge to FST out (wr) high6 81 SCKT edge to FST out (wr) low6 82 SCKT edge to FST out (wl) high 83 SCKT edge to FST out (wl) low 84 SCKT edge to data out enable from high impedance 85 SCKT edge to transmitter #0 drive enable assertion 86 SCKT edge to data out valid 87 SCKT edge to data out high impedance7 DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 49 Enhanced Serial Audio Interface Timing Table 22. Enhanced Serial Audio Interface Timing (continued) No. Characteristics1, 2, 3 Symbol -- -- -- -- -- -- -- -- -- -- Expression -- -- -- -- -- -- -- 2 x TC -- -- Min -- -- 2.0 21.0 2.0 21.0 4.0 0.0 -- -- -- -- 13.4 -- -- Max 34.0 20.0 -- -- -- -- -- -- 27.0 31.0 32.0 18.0 -- 18.0 18.0 Condition4 x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck Unit ns ns ns ns ns ns ns ns ns ns 88 SCKT edge to transmitter #0 drive enable deassertion7 89 FST input (bl, wr) setup time before SCKT edge6 90 FST input (wl) setup time before SCKT edge 91 FST input hold time after SCKT edge 92 FST input (wl) to data out enable from high impedance 93 FST input (wl) to transmitter #0 drive enable assertion 94 Flag output valid after SCKT edge 95 HCKR/HCKT clock cycle 96 HCKT input edge to SCKT output 97 HCKR input edge to SCKR output Note: 1. VCORE_VDD = 1.25 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF 2. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 3. bl = bit length wl = word length wr = word length relative 4. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that SCKT and SCKR are the same clock) 5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested 8. ESAI_1 specs match those of ESAI_0 DSP56371 Data Sheet, Rev. 4.1 50 Freescale Semiconductor Enhanced Serial Audio Interface Timing 62 SCKT (Input/Output) 63 64 78 79 FST (Bit) Out 83 FST (Word) Out 87 85 Data Out 92 Transmitter #0 Drive Enable 90 94 FST (Bit) In 91 93 94 86 89 First Bit Last Bit 87 88 84 FST (Word) In 95 Flags Out See Note Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 14 is drawn assuming positive polarity bit clock (TCKP=0) and positive frame sync polarity (TFSP=0). Figure 14. ESAI Transmitter Timing DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 51 Enhanced Serial Audio Interface Timing 62 63 SCKR (Input/Output) 64 65 66 FSR (Bit) Out 69 FSR (Word) Out 70 71 Data In First Bit 72 Last Bit 73 FSR (Bit) In 75 74 75 FSR (Word) In 76 77 Flags In Note: Figure 15 is drawn assuming positive polarity bit clock (RCKP=0) and positive frame sync polarity (RFSP=0). Figure 15. ESAI Receiver Timing HCKT 96 97 SCKT (output) Note: Figure 16 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0). Figure 16. ESAI HCKT Timing DSP56371 Data Sheet, Rev. 4.1 52 Freescale Semiconductor Digital Audio Transmitter Timing HCKR 96 98 SCKR (output) Note: Figure 17 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0). Figure 17. ESAI HCKR Timing 15 Digital Audio Transmitter Timing Table 23. Digital Audio Transmitter Timing 181 MHz No. 99 100 101 102 103 Note: 1. In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of theDSP56371 internal clock frequency. For example, if the DSP56371 is running at 181 MHz internally, the ACI frequency should be less than 90MHz. Characteristic ACI frequency (see note) ACI period ACI high duration ACI low duration ACI rising edge to ADO valid Expression Min 1 / (2 x TC) 2 x TC 0.5 x TC 0.5 x TC 1.5 x TC -- 11.1 2.8 2.8 -- Max 90 -- -- -- 8.3 Unit MHz ns ns ns ns ACI 100 103 ADO 101 102 Figure 18. Digital Audio Transmitter Timing DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 53 Timer Timing 16 Timer Timing Table 24. Timer Timing 181 MHz No. 104 105 Note: 1. VCORE_VDD = 1.25 V Characteristics TIO Low TIO High Expression Min 2 x TC + 2.0 2 x TC + 2.0 13 13 Max -- -- Unit ns ns 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF TIO 104 105 Figure 19. TIO Timer Event Input Restrictions 17 No. 106 107 108 109 110 111 112 113 114 115 GPIO Timing Table 25. GPIO Timing Characteristics1 FOSC edge to GPIO out valid (GPIO out delay time) FOSC edge to GPIO out not valid (GPIO out hold time) FOSC In valid to EXTAL edge (GPIO in set-up time) FOSC edge to GPIO in not valid (GPIO in hold time) Minimum GPIO pulse high width (except Port F) Minimum GPIO pulse low width (except Port F) Minimum GPIO pulse low width (Port F) Minimum GPIO pulse high width (Port F) GPIO out rise time GPIO out fall time TC + 13 TC + 13 6 x TC 6 x TC -- -- Expression Min -- -- 2 0 19 19 33.3 33.3 -- -- 13 13 Max 7 7 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns Note: 1. VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF 2. PLL Disabled, EXTAL driven by a square wave Figure 20. GPIO Timing DSP56371 Data Sheet, Rev. 4.1 54 Freescale Semiconductor JTAG Timing 18 No. 116 117 118 119 120 121 122 123 124 125 JTAG Timing Table 26. JTAG Timing All frequencies Characteristics Min TCK frequency of operation (1/(TC x 6); maximum 22 MHz) TCK cycle time TCK clock pulse width TCK rise and fall times TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance 0.0 45.0 20.0 0.0 0.0 0.0 5.0 25.0 0.0 0.0 Max 22.0 -- -- 10.0 40.0 40.0 -- -- 44.0 44.0 MHz ns ns ns ns ns ns ns ns ns Unit Note: VCORE_VDD = 1.25 V 0.05 V; TJ = -40C to 115C for 150 MHz; TJ = 0C to 100C for 181 MHz; CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 117 118 TCK (Input) VIH 119 VM VIL 119 118 VM Figure 21. Test Clock Input Timing Diagram DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 55 JTAG Timing TCK (Input) VIH VIL 122 123 Data Inputs 120 Data Outputs 121 Data Outputs 120 Data Outputs Input Data Valid Output Data Valid Output Data Valid Figure 22. Debugger Port Timing Diagram VIH VIL 122 TDI TMS (Input) 124 TDO (Output) 125 TDO (Output) 124 TDO (Output) Output Data Valid Output Data Valid Input Data Valid 123 TCK (Input) Figure 23. Test Access Port Timing Diagram DSP56371 Data Sheet, Rev. 4.1 56 Freescale Semiconductor Package Information 19 Package Information . SDO5_SDI0_PC6 CORE_GND CORE_VDD HCKR_PC2 SCKR_PC0 HCKR_PE2 HCKT_PC5 SCKR_PE0 SCKT_PC3 HCKT_PE5 SCKT_PE3 ADO_PD1 FSR_PC1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 SDO4_SDI1_PC7 IO_GND IO_VDD SDO3_SDI2_PC8 SDO2_SDI3_PC9 SDO1_PC10 SDO0_PC11 CORE_VDD PF8 PF6 PF7 CORE_GND PF2 PF3 PF4 PF5 IO_VDD PF1 PF0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ESAI DAX ESAI_1 61 FSR_PE1 FST_PC4 ACI_PD0 IO_GND IO_GND IO_VDD IO_VDD 60 59 58 57 56 55 54 53 52 51 50 49 FST_PE4 SDO5_SDI0_PE6 SDO4_SDI1_PE7 SDO3_SDI2_PE8 SDO2_SDI3_PE9 SDO1_PE10 SDO0_PE11 CORE_GND CORE_VDD MODA_IRQA MODB_IRQB MODC_IRQC MODD_IRQD RESET_B PINIT_NMI EXTAL PLLD_VDD PLLD_GND PLLP_GND PLLP_VDD GPIO Int/Mod 48 47 46 45 44 PLL Timer 23 24 25 26 27 28 29 43 OnCE 30 31 32 33 34 SHI 35 36 37 38 39 40 PLLA_GND 42 41 TMS TCK CORE_GND MISO_SDA IO_GND SCAN IO_VDD CORE_VDD Figure 24. DSP56371 Pinout DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 57 PLLA_VDD TDO TDI TIO0_PB0 TIO1_PB1 MOSI_HA0 SCK_SCL SS_HA2 HREQ PF9 PF10 Package Information Table 27. Signal Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Name SDO4_SDI1_PC7 IO_GND IO_VDD SDO3_SDI2_PC8 SDO2_SDI3_PC9 SDO1_PC10 SDO0_PC11 CORE_VDD PF8 PF6 PF7 CORE_GND PF2 PF3 PF4 PF5 IO_VDD PF1 PF0 GND Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name PF9 SCAN PF10 IO_GND IO_VDD TI0_PB0 TI0_PB1 CORE_GND CORE_VDD TDO TDI TCK TMS MOSI_HA0 MISO_SDA SCK_SCL SS_HA2 HREQ PLLA_VDD PLLA_GND Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name PLLP_VDD PLLP_GND PLLD_GND PLLD_VDD EXTAL PINIT_NMI RESET_B MODD_IRQD MODC_IRQC MODB_IRQB MODA_IRQA CORE_VDD CORE_GND SDO0_PE11 SDO1_PE10 SDO2_SDI3_PE9 SDO3_SDI2_PE8 SDO4_SDI1_PE7 SDO5_SD10_PE6 FST_PE4 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal Name FSR_PE1 SCKT_PE3 SCKR_PE0 IO_VDD IO_GND HCKT_PE5 HCKR_PE2 CORE_GND ADO_PD1 ADI_PD0 CORE_VDD HCKR_PC2 HCKT2_PC5 IO_GND IO_VDD SCKR_PC0 SCKT_PC3 FSR_PC1 FST_PC4 SDO5_SDI10_PC6 DSP56371 Data Sheet, Rev. 4.1 58 Freescale Semiconductor Package Information DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 59 Package Information DSP56371 Data Sheet, Rev. 4.1 60 Freescale Semiconductor Package Information DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 61 Package Information DSP56371 Data Sheet, Rev. 4.1 62 Freescale Semiconductor Design Considerations 20 Design Considerations 20.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation: T J = T A + ( P D x R JA ) Eqn. 4 Where: TA=ambient temperature C RqJA=package junction-to-ambient thermal resistance C/W PD=power dissipation in package W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. R JA = R JC + R CA Eqn. 5 Where: RJA=package junction-to-ambient thermal resistance C/W RJC=package junction-to-case thermal resistance C/W RCA=package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. * To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. * If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 63 Electrical Design Considerations As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 21 Electrical Design Considerations CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). The suggested value for a pull-up or pull-down resistor is 10 k ohm. Use the following list of recommendations to assure correct DSP operation: * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. * Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. * Route the DVDD pin carefully to minimize noise. * Use at least a four-layer PCB with two inner layers for VCC and GND. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the IRQA, IRQB, IRQC, and IRQD pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended. * Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. * Take special care to minimize noise levels on the VCCP and GNDP pins. * If multiple DSP56371 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. * RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. DSP56371 Data Sheet, Rev. 4.1 64 Freescale Semiconductor Electrical Design Considerations * At power-up, ensure that the voltage difference between the 3.3 V tolerant pins and the chip VCC never exceeds a 3.00 V. 21.1 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = CxVxf Eqn. 6 where C=node/pin capacitance V=voltage swing f=frequency of node/pin toggle Power Consumption Example For a GPIO address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 150 MHz clock, toggling at its maximum possible rate (75 MHz), the current consumption is I = 50x10 - 12 x3.3x75x10 6 = 12.375mA Eqn. 7 The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * Minimize the number of pins that are switching. * Minimize the capacitive load on the pins. One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (for example, to compensate for measured board current not caused by the DSP). Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. I/MIPS = I/MHz = (ItypF2 - ItypF1)/(F2 - F1) Eqn. 8 where : ItypF2=current at F2 ItypF1=current at F1 F2=high frequency (any specified operating frequency) F1=low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 65 Power Consumption Benchmark 22 Power Consumption Benchmark The following benchmark program permits evaluation of DSP power usage in a test situation. ;***********************************;******************************** ;* ;* CHECKS Typical Power Consumption ;******************************************************************** ORG P:$000800 move #$000000,r1 move #$000000,r0 do #1024,ldmem move r1,p:(r0) move r1,y:(r0)+ ldmem nop move #0,b1 ;jmp $FF2AE0 ;org move move move move move P:$FF2AE0 b1,y:>$100 #$FF,B #>$AF080,X0 #>$FF2AD6,r0 #$0,r1 dor #6,loop1 move p:(r0)+,x1 move x0,p:(r1)+ move x1,p:(r1)+ nop loop1 move #$0,vba move #$0,sp move #$0,sc reset move #$FFFFFF,m0 move m0,m1 move m0,m2 move m0,m3 move m0,m4 move m0,m5 move m0,m6 move m0,m7 move #>$102,ep move #>$18,sz move #>$110000,omr DSP56371 Data Sheet, Rev. 4.1 66 Freescale Semiconductor Power Consumption Benchmark move #$300,sr movep #>$F02000,X:$FFFFFF movep #$187,X:$FFFFFE ;then sets up BCR and AAR registers ;then sets up PORTB and HDI08 PORT andi #$FC,mr ;start running ROM intialisation stage ;jsr $FF1C7E ; Set green HLX zone table jsr $FF1D64 ; Run GPIONil function jsr $FF2F82 ; Initialise Green HLX jsr $FF1FA1 ; Disable DAX move #>$15F,x1 move x1,P:$FF0D7F ; Run Green HLX jmp $FF1FDB nop nop nop nop nop nop dor forever,endprog nop nop endprog nop DSP56371 Data Sheet, Rev. 4.1 Freescale Semiconductor 67 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004, 2005, 2006, 2007. All rights reserved. For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com DSP56371 Rev. 4.1, 1/2007 |
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